1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly to a semiconductor apparatus having a plurality of chips and a plurality of channels.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus, a 3-dimensional (3D) semiconductor apparatus is provided. The degree of integration of the 3D semiconductor apparatus is improved by stacking and packaging a plurality of chips in a single package. The 3D semiconductor apparatus has two or more vertically stacked chips and thus achieves a relatively high degree of integration in a limited space.
For a 3D semiconductor apparatus, a plurality of chips may be stacked and packaged in various ways. For example, a plurality of chips having the same structure may be stacked and coupled to each other through a wire, such as a metal Fine, to serve as a single semiconductor apparatus,
Under a through silicon via (TSV) scheme, as another example, a plurality of chips may be stacked and electrically coupled to each other using a via passing therethrough. Since a TSV-implemented semiconductor apparatus couples stacked chips using a via passing therethrough, it may efficiently reduce its package area compared to a wire-implemented semiconductor apparatus using a wire disposed in the border area of the stacked chips.
Each of the plurality of chips of the semiconductor apparatus may have a channel. The plurality of channels may transfer different control signals and data from one another, and the plurality of chips may independently operate,